The present invention relates generally to semiconductor device manufacturing, and, more particularly, to an apparatus and method for single die backside probing of semiconductor devices.
In the manufacture of semiconductor devices, the ability to obtain waveform measurements from internal nodes has been found to be an indispensable aspect of carrying out failure analysis and characterization. Often, active areas of the semiconductor devices are obscured by I/O (input/output) circuits, interconnect wiring, packaging, or limitations of the probing apparatus. During the integrated circuit development phase, early engineering hardware is typically characterized by subjecting the device to various test conditions such as speed, temperature, and other parameters. Measuring and diagnosing the performance of these devices is implemented by acquiring waveforms from key circuit nodes within the device such as clock signals, enable signals, address buses, and data buses. However, if the early engineering hardware does not perform adequately, or is non-functional, it then becomes important to be able to trace back signals to the source of the problem.
A convenient mode of detecting a failure source is through the use of waveform analysis. The ability to diagnose problems by waveform analysis is also significant during manufacture, as well as throughout the life of the product so that corrective action can be taken. Those skilled in the art will recognize that waveforms may be acquired from internal circuit nodes by direct-contact mechanical probing or electron beam probing. Additional techniques, such as laser-induced light, have also been utilized.
In order to prepare a device for diagnosis, electrical contact is first established with a tester and one or more of the numerous I/O circuits in the device. In some instances, these I/O circuits are placed in the periphery of the device, or located in a manner to provide some degree of access to the device's active areas by some form of mechanical or electron beam probe during operation. However, as a result of increasing circuit complexity, a trend toward higher density packaging, or the density of the I/O circuits and related probes needed to activate the device, improvements in semiconductor device access for mechanical or electron beam probe are needed.
Thus, to facilitate electrical access to the I/O of the IC, additional circuits and pads are frequently positioned adjacent to, or on the uppermost level of the IC die. Quite frequently, such IC dies with I/O circuit elements situated on the top surface have the disadvantage of obstructing internal circuitry. Additionally, packaging methods (often referred to as a “flip-chip”, “C4”, or direct chip attach (DCA)) may be attached upside-down, or flipped onto a package substrate, or directly onto a circuit board, flexible cable, or other assembly into which the IC is interconnected. As a result, the internal circuit nodes of the IC are buried and inaccessible for characterizing electrical circuit performance, performing diagnostic testing, or performing failure analysis while the IC is operating normally and in a fully functioning state. In particular, with the emergence of technologies such as embedded dynamic random access memory (eDRAM), system on a chip (SOC), and silicon on insulator (SOI) devices, for example, effective backside electrical characterization techniques are desired given the multiple wiring levels of such devices.
Additionally, in the course of performing failure analysis or diagnosing performance problems with semiconductor devices, it is often necessary to apply image based analysis techniques while exercising a chip using a test system. The chip is also referred to as the Device Under Test (DUT). Many of these image based techniques are performed through the backside of the DUT using tools that operate with wavelengths of light that pass through silicon. Backside light emission microscopy is one example of an image based technique. Presently, there are tools commercially available for performing these backside techniques on die mounted in packages or on whole wafers. However, there is currently no available means for performing backside analysis on single bare die.
A drawback in performing such a backside analysis on a packaged die stems from the fact that time and money is spent mounting the die in a suitable package. Furthermore, performing backside analysis on whole wafers is convenient up until such time the wafer is diced. At that point, the die has heretofore been required to be packaged before performing any further analysis thereon.
On the other hand, the probing of bare die presents a more difficult challenge. A conventional probe station retains the die or wafer on a flat disk (chuck), and probes are lowered onto the probe pads from above. Only the top surface of the chip is typically visible. More recently, manufacturers have introduced backside probing probe stations that utilize special probes or probe cards while the wafer is held face down on the station. Special optics are used in order to see the probe pad pattern, as well as the probe needles from the bottom. A small area of the wafer is then thinned, presumably where the defect is located, and the active area thereafter is observed using the same previously mentioned techniques. Thinning the bulk silicon on a single die or in a small region of the wafer is often necessary to improve light transmission in order to be able to observe the circuitry of a die for navigation purposes.
It is not practical to thin an entire wafer, because the resultant thickness of the wafer is insufficient to provide the mechanical rigidity necessary across an entire wafer for backside probing any die on the wafer. Accordingly, only a few select die can be thinned and observed on a given wafer. The remainder of the wafer is maintained at full thickness, thus providing mechanical stability. The selection of which particular die to thin is determined by using previous test results.
Unfortunately, there are several drawbacks associated with conventional backside probing systems. First, such systems are designed to probe an entire wafer. In other words, there is no effective means for probing individual chips. In addition, special probes and/or probe cards are needed to carry out the backside probing. Thirdly, such systems are “combination systems” in that they are built for conventional topside probing and are convertible to backside probing. As such, the switch from one type of probing to the other type typically requires factory trained personnel to reconfigure the tool after switch to a different type of probing operation.